As you may or may not know, these architectural designs are over 50 years old about now. They remain a classic. But, the components are quite difficult to find in Europe. I did manage to find a retro-style webshop which I purchased used or NOS components from!
Part list
I couldn't find all WDC CMOS versions of the 65-family of ICs, so I went with a peculiar combination:
- W65C02S (CMOS, 14 MHz)
- MOS 6522 (NMOS, 1 MHz) 'VIA'
- R6551 (NMOS, 2 MHz) 'ACIA'
- W27C020 (256 KiB) EEPROM
- AS6C62256 (32 KiB) SRAM
- SN74LS00N NANDs
Given that I have a 1 MHz crystal oscillator, this runs fine. I'm using an LM7805 fixed 5V voltage regulator to power this through a 9V battery or a variable power source. There's a slight but acceptable voltage drop of less than 300 mV throughout the circuit. A 1.8432 MHz crystal resonator is used for the ACIA to use as baudrate generation.
Memory map
The memory map of this breadboard computer is similar to Ben Eater's architectural design, as it made a lot of sense for this build. It has the added benefit to immediately use their adapted Apple I Wozmon implementation. Ben Eater produces great explanational videos, and is generally a good person; I do recommend supporting them and their work.
That being said, the memory map consists of:
0000 - 3FFF :SRAM (16k)4000 - 7FFF :I/O (16k)8000 - FFFF :EEPROM (32k)
Currently, the I/O space is decoded lazily, with two I/O devices being present on the bus:
5000 - 5003 :6551 Asynchronous Communication Interface Adapter (ACIA)6000 - 600F :6522 Versatile Interface Adapter (VIA)
The NANDs are used for inverting the A15 signal (for active low EEPROM enable and used in the I/O enable), I/O enable (low A15 and high A14, for enabling the I/O address space), as well as write clock synchronisation with the SRAM.
